Design Verification Engineer

Design Verification Engineer responsible for requirements-based and coverage-driven verification of FPGA and airborne electronic hardware in compliance with DO-254.

Job Requirements

• Bachelor’s degree in Engineering, Computer Engineering, Electrical Engineering, Computer Science, or a related STEM field.

• Minimum 5 years of relevant design verification experience, or an advanced degree with related experience.

• Experience with FPGA design verification.

• Experience with DO-254 development and verification processes.

• Experience developing testbenches and verification environments using SystemVerilog, VHDL, and/or Verilog.

• Experience with requirements-based verification and requirements traceability.

• Experience performing ASIC, FPGA, or SoPC verification using simulation, analysis, inspection, and hardware test methods.

• Experience with verification and simulation tools such as:

  • QuestaSim

  • Vivado

  • Libero

  • Synplify Pro

• Experience with functional, code, and assertion coverage analysis.

• Experience verifying clock domain crossings and device-level timing constraints.

• Knowledge of digital interfaces such as PCIe, DDR, Ethernet, I2C, ARINC 429, and CAN.

• Experience with scripting or programming languages such as Python, Perl, Linux shell, or C/C++.

Preferred Skills

• Strong experience with UVM.

• Experience with constrained-random verification methodology.

• Experience with DO-254 DAL A verification activities.

• Experience generating certification artifacts for airborne electronic hardware.

• Experience with linting and CDC analysis.

• Experience with Logical Equivalence Checking (LEC).

• Experience with regression automation.

• Experience with reusable verification components, sequences, and coverage models.

• Experience supporting FAA Stage of Involvement audits.

• Experience with video or networking technologies.

• Experience estimating verification scope, effort, schedule, and resource requirements.

• Experience supporting technical proposals, RFIs, or RFPs.

• Experience mentoring junior verification engineers.

Job Responsibilities

• Develop verification plans based on system and hardware requirements.

• Perform requirements capture, decomposition, and traceability activities.

• Architect and implement constrained-random and directed verification environments.

• Develop and maintain reusable UVM/SystemVerilog testbenches, sequences, verification components, and functional coverage models.

• Perform FPGA, ASIC, and SoPC verification using simulation, inspection, analysis, and hardware testing.

• Execute functional, code, and assertion coverage analysis.

• Drive verification coverage closure against defined requirements.

• Perform linting, clock domain crossing analysis, LEC, assertion-based verification, and regression testing.

• Review RTL architecture, interface specifications, and digital implementations for verification completeness and testability.

• Verify timing behavior and device-level timing constraints.

• Generate DO-254 verification documentation and certification artifacts.

• Support DO-254 DAL A compliance and certification activities.

• Participate in technical peer reviews and certification audits.

• Develop verification automation scripts and test utilities.

• Support integration and hardware-level verification activities.

• Provide technical direction to junior verification engineers.

• Support verification planning, estimation, risk tracking, and project execution activities.

Pay Details: $46.00 to $62.00 per hour

Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.

Equal Opportunity Employer/Veterans/Disabled

Military connected talent encouraged to apply

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• The California Fair Chance Act
• Los Angeles City Fair Chance Ordinance
• Los Angeles County Fair Chance Ordinance for Employers
• San Francisco Fair Chance Ordinance

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